1. Field of the Invention
The present invention relates to an on-screen display apparatus and on-screen display method for displaying a character (including a symbol and a pattern) or a test pattern instead of or over an input image signal so as to adjust a picture quality or a screen of a television, a display or the like.
2. Description of Related Art
FIG. 1 is a block diagram showing a principal portion of a conventional on-screen display apparatus which is shown, for example, in a block diagram on p. 931, "Information/Acoustic/Visual IC" (DB52-00931-1), Fujitsu Semiconductor Device Data Book, 1993.
In FIG. 1, denoted at 1 is a dot clock generating part. In response to a horizontal synchronizing signal HSYNC, the dot clock generating part 1 generates a dot clock signal CLKD for each dot in a horizontal direction of a character and outputs the dot clock signal CLKD to a horizontal position control part 3 and a vertical/horizontal character size control part 4. A vertical position control part 2 receives a vertical synchronizing signal VSYNC and outputs an output signal RV to the vertical/horizontal character size control part 4, to thereby control a vertical display position of a character on an on-screen display screen. In accordance with the signal CLKD from the dot clock generating part 1 and the horizontal synchronizing signal HSYNC, the horizontal position control part 3 controls a horizontal display position of a character on an on-screen display screen. Receiving the output RV from the vertical position control part 2 and an output signal RH from the horizontal position control part 3, the vertical/horizontal character size control part 4 controls the signals CLKD and RH by frequency-division so as to adjust a horizontal dot number and a vertical dot number (i.e., character size) of a character which is formed on the display screen. The vertical/horizontal character size control part 4 then outputs signals RV1 and RH1 to a timing generating part 5.
In response to the signals RV1 and RH1, the timing generating part 5 generates various types of timing signals which are to be supplied to the on-screen display apparatus and outputs the timing signals to a read address counter 6, a display memory RAM 7, a character generator ROM 8 and a shift register 9. The read address counter 6 generates a memory read address signal which is needed for on-screen display of a character on the screen. The display memory RAM 7 stores face data which is formed by codes of a character which is to be displayed on-screen. The character generator ROM 8 stores font data which corresponds to the face data which is stored in the display memory RAM 7. An output font signal I)C which corresponds to output face data DD outputted from the display memory RAM 7 is outputted from the character generator ROM 8 to the shift register 9. The shift register 9 performs parallel/serial conversion on the output font signal DC outputted from the character generator ROM 8 and outputs the signal bit by bit. A display control part 10 performs display attribute control on an output signal SC outputted from the shift register 9 to turn on and off Reverse (I), Red (R), Green (G) and Blue (B), etc.
FIG. 2 is a block diagram showing a structure of the vertical/horizontal character size control part 4 and the read address counter 6. The vertical/horizontal character size control part 4 comprises a horizontal character size control part 11 and a vertical character size control part 12. The horizontal character size control part 11 divides the frequency of the dot clock CLKD from the dot clock generating part 1 by an integer to control the character size in the horizontal direction. The vertical character size control part 12 divides the frequency of the signal RH from the horizontal position control part 3 by an integer to control the character size in the vertical direction.
The read address counter 6 comprises a horizontal character dot counter 13, a horizontal character address counter 14, a vertical character dot counter 15 and a vertical character address counter 16. Through the timing generating part 5, the horizontal character dot counter 13 receives a signal which is obtained b: dividing the frequency of the dot clock CLKD by an integer by the character size control part 11, and generates a pulse for each character while counting the number of dots of the character in the horizontal direction. Pulses from the horizontal character dot counter 13 are supplied to the horizontal character address counter 14. The horizontal character address counter 14 counts the pulses and generates an on-screen horizontal direction address of the character. Through the timing generating part 5, the vertical character dot counter 15 receives a signal which is generated by the vertical character size control part 12. The vertical character dot counter 15 counts the number of dots of the character in the vertical direction and outputs a signal to the vertical character address counter 16. The vertical character address counter 16 counts the signal from the vertical character dot counter 15 and generates a vertical direction address of the character.
In such a conventional on-screen display apparatus, the horizontal synchronizing signal HSYNC is supplied to the dot clock generating part 1, so that the dot clock generating part 1 generates a dot clock for forming dots of a character in the horizontal direction, i.e., the dot clock CLKD) which is equal to the frequency of the horizontal synchronizing signal HSYNC as it is multiplied by an integer and which synchronizes with the horizontal synchronizing signal HSYNC. The horizontal synchronizing signal HSYNC is also supplied to the horizontal position control part 3, so that the dot clock CLKD generated by the dot clock generating part 1 is counted for an optional number of times and the horizontal reset signal RH which has been adjusted for a horizontal phase is obtained. The horizontal reset signal RH is used to control the starting position of displaying the character on the display screen in the horizontal direction. On the other hand, the vertical synchronizing signal VSYNC is supplied to the vertical position control part 2, so that the signal RH from the horizontal position control part 3 is counted for an optional number of times and the vertical reset signal RV which has been adjusted for a vertical phase is obtained. The vertical reset signal RV is used to control the starting position of displaying the character on the display screen in the vertical direction.
The horizontal character size control part 11 divides the frequency of the dot clock CLKD by an integer to multiply the dot number of the character in the horizontal direction by an integer. In a similar manner, the vertical character size control part 12 divides the frequency of the signal RH from the horizontal position control part 3 by an integer to multiply the dot number of the character in the vertical direction by an integer. Controlling in this manner, a character is displayed on the screen as having a length doubled in the horizontal direction when only the horizontal character size control part 11 is set to divide a frequency into half, but as having a length doubled in the vertical direction when only the vertical character size control part 12 is set to divide a frequency into half, as shown in FIG. 3, for instance. When both the horizontal character size control part 11 and the vertical character size control part 12 are set to divide a frequency into half, the character is displayed on the screen as doubled in both the horizontal and the vertical direction.
Receiving the output signals RV1 and RH1 from the vertical/horizontal character size control part 4, the timing generating part 5 generates various types of timing pulses which are needed for subsequent on-screen displaying and control operations.
In the read address counter 6, as described above, a clock obtained by frequency-division performed by the horizontal character size control part 11 is supplied to the horizontal character dot counter 13 through the timing generating part 5, so that the horizontal character dot counter 13 counts a horizontal direction dot number NH of the character. An output from the horizontal character dot counter 13 is supplied to the horizontal character address counter 14, and the horizontal character address counter 14 counts a horizontal direction character number MH on the screen and generates a horizontal direction display address of the character on the display screen. A signal from the vertical character size control part 12 is supplied to the vertical character dot counter 15 through the timing generating part 5 and the vertical character dot counter 15 counts a vertical direction dot number (hereinafter "vertical dot number") NV of the character. An output from the vertical character dot counter 15 is supplied to the vertical character address counter 16. The vertical character address counter 16 counts a vertical direction character number (hereinafter "vertical character number") MV on the screen and generates a vertical direction display address of the character on the display screen. In such a structure, as shown in FIG. 4, a character area is formed which measures MH characters in the horizontal direction with NH dots for each character and MV characters in the vertical direction with NV dots for each character.
In response to a display memory write address signal supplied from a microcomputer bus or the like, the display memory RAM 7 writes face data of on-screen display on a display memory map which corresponds to the screen. Further, in response to a memory read address signal RA generated by the read address counter 6, the face data DD which has been written in the display memory RAM 7 is read.
Data structure in the display memory RAM 7 can be expressed as shown in FIG. 5, for example. In FIG. 5, a character cede of Nd bits is written in a memory map area which corresponds to a display area on the screen and which measures MH characters in the horizontal direction and MV characters in the vertical direction. In response to the memory read address signal RA, the character cede of Nd bits is read in parallel to the face data DD.
While ASCII codes are generally well known as character codes, the character codes in the present invention are those which are described in "Information/Acoustic/Visual IC" (DB52-00931-1), p. 961, Fujitsu Semiconductor Device Data Book, 1993. In accordance with such face data DD, the font data DC written in the character generator ROM 8 is read.
The font data DC of Nd bits outputted in parallel in the horizontal direction from the character generator ROM 8 is parallel/serial converted by the shift register 9, whereby the time series font signal SC is obtained. This font signal SC is supplied to the display control part 10 and outputted as on-screen display signals RO, GO and BO which are controlled for attributes independently of R, G and B.
The display control part 10 has a circuit structure as that shown in FIG. 6, for instance. Denoted at 17 is an exclusive OR gate for reversing the font signal SC which is supplied thereto. The font signal controlled for reversing by the exclusive OR gate 17 is supplied to AND gates 18, 19 and 20. In such a display control part 10, the font signal SC is processed by non-reverse/reverse control based on the input control signal SI supplied to one terminal of the exclusive OR gate 17, and outputted independently of R, G and B as the on-screen outputs RO, GO and BO which are ON/OFF controlled by input control signals SR, SG and SB supplied to one terminals of the AND gates 18, 19 and 20.
In such a conventional on-screen display apparatus, attributes of a character to be displayed on the screen are changed in accordance with the signals SI, SR, SG and SB. However, in most cases, the signals SI, SR, SG and SB are controlled by a control signal which is stored in a memory or the like which is disposed outside the on-screen display apparatus. Where a control operation is provided in such a manner, it is difficult to set different attributes for each character which is to be displayed on the screen. For example, it is likely that attributes are controlled per screen only.
An on-screen display apparatus in which it is possible to switch attributes of any wanted character in one screen picture is desired in order to more efficiently perform on-screen display of a number of menu screens or the like which are displayed for adjustment of a picture quality and a screen of a television and a display which have advanced functions and adjustable items.
FIG. 7 is a block diagram showing other structure of a conventional on-screen display apparatus. This is an on-screen display apparatus which can control displaying character by character. In FIG. 7, denoted at 21 is an attribute control memory RAM which writes and reads in accordance with address signals and control signals which are similar to those used for the display memory RAM 7. The on-screen display apparatus is otherwise similar to the conventional apparatus described with reference to FIG. 1, and therefore, a redundant description will be omitted.
In such a on-screen display apparatus, the attribute control memory RAM 21 is expressed as shown in FIG. 8 just like the structure of the display memory RAM 7 is expressed as shown in FIG. 5. Hence, during reading of character code data for on-screen displaying from the display memory RAM 7, a display control signal which is related to the character (hereinafter "attribute data signal") is also read. By connecting the attribute data signal to the non-reverse/reverse control signal SI and control signals SR, SG and SB for controlling ON/OFF of R, G and B which are supplied to the display control part 10, the on-screen display apparatus changes attributes of each character.
Further, some other conventional on-screen display apparatuses not only display attributes of characters as above but also perform a function of a test pattern generating circuit which displays a test pattern signal having a gradation such as a stepped wave and a window signal.
FIG. 9 is a block diagram showing other structure of a conventional on-screen display apparatus which additionally has a function of a test pattern generating circuit. In FIG. 9, denoted at 22 is a test pattern generating part which receives a timing signal which is generated by the timing generating part 5 and which is synchronized with a displayed screen, to thereby generate a test signal having a gradation such as a stepped wave and a window signal. A digital signal outputted from the test pattern generating part 22 is supplied to a digital/analog convertor 23. Outputs RT, GT and BT from the digital/analog convertor 23 are supplied to an R-adder 24, a G-adder 25 and a B-adder 26. The on-screen signals RO, GO and BO regarding R, G and B from the display control part 10 are supplied to the R-adder 24, the G-adder 25 and the B-adder 26, respectively to be added. The on-screen display apparatus is otherwise similar to the conventional apparatus described with reference to FIG. 1, and therefore, a redundant description will be omitted.
In such an on-screen display apparatus, the test pattern generating part 22 for generating a test pattern signal which is needed to adjust a screen is disposed independently, for example. Hence, a digital test signal from the test pattern generating part 22 is digital/analog converted into an analog signal by the digital/analog convertor 23, and the R-adder 24, the G-adder 25 and the B-adder 26 add the converted signals RT, GT and BT to the font signals RO, GO and BO which have controlled display. As a result, the output signals RS, GS and BS are obtained.
Accurate signal generation is possible if the test pattern generating part 22 is formed by "a gradation memory RAM" which is similar to the attribute control memory RAM 21 which was described with reference to FIG. 8 showing the conventional technique as the means for generating a signal having a gradation at an optional position in the screen. Test pattern signals generated by the gradation memory RAM include a color bar, a stepped wave and a window signal. Not only generating a test pattern signal, the gradation memory RAM my have various features to generate a color gradation signal which can be displayed with the test pattern signal on the screen.
The conventional on-screen display apparatus as above has the following problems.
Now, it is assumed that the conventional on-screen display apparatus displays a picture as that shown in FIG. 10 in response to an NTSC (national television system committee) signal, for example. When an input signal is switched with an extended definition television (EDTV) signal for performing twice as much as scanning realized by the NTSC signal (i.e., an EDTV signal to which twice as many as scanning lines of the NTSC signal are assigned) in a state where the frequency-division ratio of the vertical/horizontal character size control part 4 is fixed, as shown in FIG. 11, the number of the scanning liens is doubled in a display area per character. Hence, the position of a character changes and the size of the character is reduced to half as compared with the case shown in FIG. 10.
To deal with this, the vertical character size control part 12 divides into half the frequency of a signal supplied from the horizontal position control part 3, doubling the vertical dot number of the character. As a result, the character is displayed on the screen at the same vertical position and with the same character size as in the case here an NTSC signal is supplied.
Thus, when the number of the scanning lines of an inputted synchronizing signal changes simply by a factor of an integer as the relationship between an NTSC signal and an EDTV signal, it is possible to maintain the position and the size of a character constant on the screen under the control of the vertical character size control part 12. However, if the number of the scanning lines of an inputted signal is not an integer-multiplication of that of a reference signal, no matter how the frequency-division is switched by the vertical character size control part 12, it is impossible to maintain the position and the size of a character constant on the screen and to maintain the number of characters displayed on the screen constant. Further, neither the vertical size of each character is constant. Due to this, when a menu screen for adjustment of a screen, for instance, is to be displayed, the position of the menu screen changes, some characters become missing on the screen or other problems occur.
To control attributes of each character, the conventional on-screen display apparatus of FIG. 7 additionally needs the attribute control memory RAM 21 which corresponds to control bits for the display control part. Although the attribute control memory RAM 21 uses four bits to deal with the attributes SI, SR, SG and SB in this conventional technique, it is necessary to additionally expand bits if a further attribute is needed, which increases a cost.
The gradation memory RAM which serves as the test pattern generating part 22 needs additional 6 to 8 bits, for example, to obtain a gradation characteristic which is needed for a test signal. This also increases a cost.